Job Details:

Job Description:

Position Overview

We are seeking a Layout Design Engineer to design and optimize custom physical layouts for analog, mixed-signal, and memory circuits in advanced CMOS technology. This role focuses on creating high-quality layouts that meet stringent performance, area, and reliability requirements while collaborating closely with circuit designers to achieve functional and performance specifications.

Key Responsibilities

Custom Layout Design & Optimization

• Plan, design, and validate highly customized physical layouts using Virtuoso XL for analog, mixed-signal, and memory circuits
• Optimize layouts to meet performance, area, and reliability goals across advanced CMOS technology nodes
• Leverage best-known methods and industry practices to create high-quality layouts efficiently
• Implement design hierarchy and hierarchical layout integration strategies

Cross-Functional Collaboration & Validation

• Collaborate closely with circuit designers to understand and meet functional and performance specifications
• Work with process engineers and design teams to ensure manufacturability and yield optimization
• Participate in design reviews and provide layout expertise for circuit optimization
• Support design validation through comprehensive layout verification processes

Design Rule Compliance & Quality Assurance

• Ensure compliance with design rules using DRC/LVS verification methodologies
• Implement fill strategies to meet design rules and manufacturing requirements within layout blocks
• Develop and execute layout floorplans that optimize circuit performance and area utilization
• Maintain high standards for layout quality and design integrity

Core Competencies

• Strong problem-solving and analytical skills for complex layout challenges
• Excellent teamwork and collaboration abilities
• Attention to detail and commitment to design quality
• Effective communication skills for cross-functional collaboration

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field of study
• Strong foundation in integrated circuit design principles and CMOS technology
• Experience with industry-standard EDA tools, DRC/LVS verification, and CMOS process technologies
• Experience with design hierarchy, hierarchical layout integration, and layout floorplanning techniques
• Experience with basic integrated circuit operation and analog/mixed-signal design principles
• Working in Unix/Linux environment for design tool operation
• Advance English level.
• Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred Qualifications

• Post Graduate degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field of study
• Experience in device-level CMOS analog/memory custom layout design
• Experience with advanced process nodes (7nm and below)
• Experience with VLSI design principles and methodologies
• Experience with ICC, Fusion Compiler, and ICWBEV+ design tools
• Experience in scripting languages (Python, SKILL) for design automation
• Experience with Berkeley Analog Generator for automated layout generation
• Experience in advanced layout techniques for high-performance circuits

What We Offer

• Opportunity to work on cutting-edge analog and mixed-signal circuit designs
• Access to advanced EDA tools and state-of-the-art process technologies
• Collaboration with world-class circuit designers and layout engineers
• Professional development in advanced layout design techniques
• Direct impact on Intel's leading-edge semiconductor products

A candidate who accepts an offer of employment in Mexico is required to present their own personal identification information and numbers for the following: Mexican Security Number (NSS), Tax Identification Number (RFC) and CURP identification number.

Job Type:

College Grad

Shift:

Shift 1 (Mexico)

Primary Location:

Mexico, Guadalajara

Additional Locations:

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.